High-rate, Low Power Sst (scarce State Transition) Scheme Viterbi Decoder Employing 4-way Acs Units
نویسندگان
چکیده
Viterbi decoders employed in digital wireless communications are complex and dissipate large amount of power. In this paper, we investigate power dissipation of Radix-4 Viterbi decoder and SST (Scarce State Transition) Radix-4 Viterbi decoder with changing the constraint length K (namely, K=3, 4). We presents a low power, high-rate Viterbi decoder using SST scheme and Radix-4 trellis. The SST makes it possible to omit the maximum likelihood decision (MLD) circuit[1, 6]. Radix-4 trellis, consisting of four 4-way ACS (Add-Compare-Select) units, is based on a restructuring of the conventional Radix-2 trellis into a Radix-4 trellis[2]. We designed the behavior of two Viterbi decoders in VHDL and synthesized using a synthesis tool. Power estimation obtained through gate level simulations indicates that the proposed design reduces the power dissipation of a Radix-4 Viterbi decoder design by 33%.
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